The present invention relates to a converter, and more particularly, to a multi-phase DC—DC converter and a control circuit for a multi-phase DC—DC converter.
Japanese Laid-Open Patent Publication Nos. 2000-308337, 2002-044941, and 2003-284333 each describe an example of a conventional multi-phase DC—DC converter, in which a plurality of DC—DC converters are connected in parallel and each converter is operated at a different switch timing (phase).
Methods for controlling a DC—DC converter include separate-excitation and self-excitation. With separate-excitation, a DC—DC converter performs a switching operation in synchronization with a clock signal (separately-excited DC—DC converter). With self-excitation, a DC—DC converter operates based on a time constant of the system of the converter (self-excited DC—DC converter). First, a self-excited DC—DC converter and a separately-excited DC—DC converter will be described, and then a multi-phase DC—DC converter will be described.
FIG. 1 is a schematic circuit diagram of a separately-excited DC—DC converter 100. The DC—DC converter 100 includes a control unit 1a and a converter unit 90. The converter unit 90 includes an output transistor T1, a synchronous rectifier transistor T2, a choke coil L1, a current detection resistor Rs1, and a smoothing capacitor C1. The output transistor T1 is configured by an N-channel MOS (metal oxide semiconductor) transistor. The synchronous rectifier transistor T2 is configured by an N-channel MOS transistor.
The control unit 1a generates output signals DH1 and DL1, which are complementary to each other, and provides the gate of the output transistor T1 with the output signal DH1 and the gate of the synchronous rectifier transistor T2 with the output signal DL1.
The drain of the output transistor T1 is supplied with an input voltage Vi. When the output signal DH1 rises to a high (H) level, the output transistor T1 is turned on. This outputs an output voltage Vo via the choke coil L1 and the current detection resistor Rs1. When the output signal DL1 rises to an H level, the synchronous rectifier transistor T2 is turned on. This outputs the energy accumulated in the choke coil L1 as the output voltage Vo. The output voltage Vo is smoothed by the smoothing capacitor C1.
The control unit 1a is supplied with the input voltage Vi as a power supply Vcc. The voltage of the two terminals of the current detection resistor Rs1 is applied to a voltage amplifier 2 included in the control unit 1a. The voltage amplifier 2 amplifies a voltage generated between the two terminals of the current detection resistor Rs1 in accordance with an output current flowing through the current detection resistor Rs1 and provides a comparator 3 with an amplification signal.
An error amplifier 4 included in the control unit 1a amplifies the voltage difference between a divided voltage, which is obtained by resistors R1 and R2 dividing the output voltage Vo with the voltage of a reference power supply e1, and provides the comparator 3 with an amplification signal. The voltage of the reference power supply e1 is set to coincide with the divided voltage obtained by the resistors R1 and R2 when the output voltage Vo reaches a specified value.
The comparator 3 compares the voltage of the amplification signal from the voltage amplifier 2 with the voltage of the amplification signal from the error amplifier 4. When the voltage of the amplification signal from the voltage amplifier 2 is higher than the voltage of the amplification signal from the error amplifier 4, the comparator 3 provides a reset terminal R of a flip-flop circuit 6 with an output signal having an H level. When the voltage of the amplification signal from the voltage amplifier 2 is lower than the voltage of the amplification signal from the error amplifier 4, the comparator 3 provides the reset terminal R with an output signal having a low (L) level.
An oscillator 5 provides a set terminal S of the flip-flop circuit 6 with a pulse signal having a fixed frequency. The flip-flop circuit 6 generates an output signal Q having an H level and an output signal /Q having an L level when its set terminal S is provided with a pulse signal having an H level. The flip-flop circuit 6 generates an L level output signal Q and an H level output signal /Q when its reset terminal R is provided with an H level pulse signal. The output signal Q of the flip-flop circuit 6 is the output signal DH1 of the control unit 1a, and the output signal /Q of the flip-flop circuit 6 is the output signal DL1 of the control unit 1a. 
The control unit 1a turns on the output transistor T1 in fixed cycles in response to the rise of a pulse signal provided from the oscillator 5. When the output transistor T1 is turned on, the current flowing through the choke coil L1 and the current detection resistor Rs increases, and the voltage of the amplification signal of the voltage amplifier 2 increases. When the voltage of the amplification signal of the voltage amplifier 2 increases above the voltage of the amplification signal of the error amplifier 4, the reset terminal R of the flip-flop circuit 6 is provided with an H level signal. As a result, the output transistor T1 is turned off, the synchronous rectifier transistor T2 is turned on, and energy accumulated in the choke coil L1 is output.
If the output voltage Vo decreases when the output transistors T1 and T2 are turned on or off, the voltage of the amplification signal of the error amplifier 4 becomes higher than the voltage of the amplification signal of the voltage amplifier 2. In this case, a relatively long time is required for the output signal of the comparator 3 to rise to an H level. This extends the on-time of the output transistor T1.
When the output voltage Vo increases, the voltage of the amplification signal of the error amplifier 4 becomes lower than the voltage of the amplification signal of the voltage amplifier 2. In this case, the time required for the output signal of the comparator 3 to rise to an H level is short. This shortens the on-time of the output transistor T1.
The output transistor T1 is turned on in fixed cycles in accordance with the frequency of a pulse signal provided from the oscillator 5. The timing at which the output transistor T1 is turned off is determined in accordance with an increase in the output current. The off timing of the transistor T1 is changed in accordance with an increase or a decrease in the output voltage Vo to keep the output voltage Vo constant.
FIG. 2 is a schematic circuit diagram of a self-excited DC—DC converter 200. The DC—DC converter 200 includes a converter unit 90, which is the same as the converter unit 90 included in the DC—DC converter 100 shown in FIG. 1.
A comparator 7 included in a control unit 1b compares a divided voltage, which is obtained by resistors R1 and R2 dividing an output voltage Vo with the voltage of a reference power supply e1. The voltage of the reference power supply e1 is set to coincide with the divided voltage obtained by the resistors R1 and R2 when the output voltage Vo reaches a specified value. When the divided voltage obtained by the resistors R1 and R2 is higher than the voltage of the reference power supply e1, the comparator 7 generates an L level output signal. When the divided voltage obtained by the resistors R1 and R2 is lower than the voltage of the reference power supply e1, the comparator 7 generates an H level output signal.
A one-shot flop—flop circuit 8 receives an output signal from the comparator 7 and generates signals Q and /Q, which are complementary to each other. The one-shot flip-flop circuit 8 generates an H level output signal Q for a fixed time in response to an H level output signal from the comparator 7.
The output signal Q of the one-shot flip-flop circuit 8 is provided to the gate of an output transistor T1 as an output signal DH1, and the output signal /Q of the flip-flop circuit 8 is provided to the gate of a synchronous rectifier transistor T2 as an output signal DL1.
In the DC—DC converter 200, which fixes the on-time of the transistor T1, the output voltage Vo increases when the output transistor T1 is turned on, and energy accumulated in the choke coil L1 is discharged when the output transistor T1 is turned off. When the energy accumulated in the choke coil L1 decreases, the output voltage Vo decreases and the divided voltage obtained by the resistors R1 and R2 decreases below the voltage of the reference power supply e1. In this case, the one-shot flip-flop circuit 8 generates an H level output signal Q for a fixed time so that the transistor T1 is turned on and maintained to be on for the fixed time. With this operation, the output voltage Vo is maintained to be a constant voltage based on the reference power supply e1. The on-time of the output transistor T1 is fixed irrespective of a period in which the output voltage Vo is changing. However, when the output voltage Vo decreases, the off-time of the output transistor T1 is shortened. As a result, the switching frequency of the output transistor T1 changes in accordance with the output voltage Vo.
FIG. 3 is a schematic circuit diagram of a multi-phase DC—DC converter 300 having two phases. Converter units 9a and 9b are the same as the converter unit 90 shown in FIG. 1. A smoothing capacitor C1 is shared by the two converter units 9a and 9b. 
A control unit 1c includes a voltage amplifier 2a, a voltage amplifier 2b, a comparator 3a, a comparator 3b, a flip-flop circuit 6a, and a flip-flop circuit 6b. The voltage amplifier 2a amplifies a voltage between the two terminals of a current detection resistor Rs1. The voltage amplifier 2b amplifies a voltage between the two terminals of a current detection resistor Rs2. The comparator 3a compares an output voltage of the voltage amplifier 2a with an output voltage of an error amplifier 4. The comparator 3b compares an output voltage of the voltage amplifier 2b with an output voltage of the error amplifier 4. The flip-flop circuit 6a generates output signals DH1 and DL1 for controlling the converter unit 9a in accordance with an output signal of the comparator 3a. The flip-flop circuit 6b generates output signals DH2 and DL2 for controlling the converter unit 9b in accordance with an output signal of the comparator 3b. 
An oscillator 5a provides a set terminal S of each of the flip-flop circuits 6a and 6b with a pulse signal. The oscillator 5a alternately provides the flip-flop circuits 6a and 6b with two pulse signals. Thus, the frequency of the pulse signal of the oscillator 5a is substantially twice the frequency of the pulse signal of the oscillator 5 shown in FIG. 8.
Each of the converter units 9a and 9b is operated by the control unit 1c at the same frequency as in the current-mode type DC—DC converter 100 shown in FIG. 1. However, the flip-flop circuits 6a and 6b operate in accordance with two pulse signals having phases deviating from each other by 180 degrees. Thus, the converter units 9a and 9b operate at a frequency substantially twice the operating frequency of their load.